1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, a technique for achieving high-speed operation and a sufficient operating margin of a semiconductor memory having a dual operation function.
2. Description of the Related Art
Recently, the flash memory has come into wide use as an electrically rewritable semiconductor memory device. The flash memory is categorized into the NAND type used for data storage that is typically the memory card, and the NOR type that stores a program and is built in electronic devices. The typical NOR type flash memory stores data (“1” or “0”) based on whether the charge is stored in the floating gate. The unit cell of the NOR type flash memory is composed of a single MOS transistor, which is equipped with a control gate (upper gate) and a floating gate (lower gate).
In read operation in which data is read from a specified memory cell, a positive bias (for example, 5 V) is applied to the control gate of the selected memory cell, and a bias approximately equal to 1 V is applied to the drain thereof from the sense amplifier. The charge stored in the floating gate cancels the bias applied to the control gate, and the memory cell does not allow current to pass therethrough, so that (nonconducting) data “0” can be read. In contrast, when no charge is in the floating gate, the charge is not canceled by the bias applied to the control gate, and the memory cell allows current to pass therethrough, so that (conducting) data “1” can be read. The sense amplifier senses the current thus produced, and selectively voltages corresponding to “0” and “1”. At that time, as the difference between cell current Ic1 for data “1” and cell current Ic0 for data “0” becomes greater, the sense amplifier reads data more easily, so that the semiconductor device can operate faster with the greater operating margin.
FIG. 1 is a block diagram of a configuration of the sense amplifier. A selected memory cell 11a is connected to a sense amplifier 13a via a decoder 12a. A reference cell 11b for data reference is connected to a sense amplifier 13b via a decoder 12b. The sense amplifiers 13a and 13b are connected to a differential sense amplifier 17, so that the memory cell 11a can be operatively coupled with the reference cell 11b. In FIG. 1, reference numerals 14a and 14b, 15a and 15b, and 16a and 16b indicate source switches, parasitic resistances, and grounds (GND) respectively connected to the memory cells 11a and 11b. 
There is the parasitic resistance 15a between the memory cell 11a and GND 16a due to an interconnection line provided therebetween. When cell current Ic flows through the parasitic resistance 15a, the potential of the source switch 14a connected to the memory cell 11a is not the GND level but is equal to Vs (=Ic·R) where Vs is the product of the resistance value R and the cell current Ic. Generally, the memory cell is n-channel transistor, and the cell current Ic is described as Ic=β·Vds(Vgs−Vt−Vds/2) where β is the proportionality constant, Vgs is the gate-source voltage, Vds is the drain-source voltage, and Vt is the threshold voltage. According to the above equation, as the source potential Vs raises, the gate-source voltage Vgs and the drain-source voltage Vds decrease, so that the cell current Ic is decreased. With the miniaturization of the device, the cell current Ic inevitably decreases. Thus, as the device is more miniaturized, the read operation is more affected by variation of the source potential Vs.
In the conventional flash memory, data rewriting is slow and the usability is poor as compared to the DRAM or SRAM because of the following. In the flash memory, read operation by the processor is not allowed when programming or erasing is in progress. The status register of the flash memory should be periodically checked by polling in order to determine whether programming or erasing is completed prior to the read operation on the flash memory. The dual operation function copes with these problems and allows data to be read while data is programmed or erased (rewritten).
FIG. 2 is a block diagram of an internal configuration of the conventional flash memory equipped with the dual operation function that enables simultaneous operations. In this configuration, the memory cell array is divided into several banks (four banks in the present example). When one of the banks is involved in data rewriting, data can be simultaneously read from another bank.
A memory cell array 200 has four banks, namely, a zeroth bank 201, first bank 202, second bank 203 and third bank 204. The memory cell array 200 further includes read address switches and write address switches (AR0-AR3 and AW0-AW3) for address read (AR) and address write (AR), read data switches and data write switches (DR0-DR3 and DW0-DW3) for data read (DR) and data write (DW), source switches S0-S3, a data read sense amplifier block 207, a data write sense amplifier block 208, an address buffer 209, a controller 210, and I/O terminals 213. The read address switches AR0-AR3 are respectively provided to the banks, and the write address switches AW0-AW3 are respectively provided to the banks. The read data switches DR0-DR3 are respectively provided to the banks, and the write data switches DW0-DW3 are respectively provided to the banks. The source switches S0-S3, which are respectively provided to the four banks and are connected to a ground terminal 212, function to connect the banks to a read reference 205 and/or a write reference 206. The data read sense amplifier block 207 has a data read sense amplifier 207a, and an output circuit 207b, and is connected to the read reference 205. The data write sense amplifier block 208 includes a write sense amplifier 208a, a write circuit 208b, and an erase circuit 208c, and is connected to the write reference 206. The address buffer 209 is connected to address terminals 211 and is accessible to the four banks. The controller 210 is connected to the data read sense amplifier block 207, the data write sense amplifier block 208, and the address buffer 209. The I/O terminals 213 are connected to the output circuit 207b of the data read sense amplifier block 207 and the write circuit 208b of the data write sense amplifier block 208.
The memory cell array 202 has a configuration that realizes the dual operation function in which data can be read when programming or erasing is in progress. This configuration enables each of the banks 201-204 to be selectively connected to the read circuit and the write circuit. More specifically, one of the banks is connected to the read circuit, and another bank is simultaneously connected to the write circuit. Then, the read operation is executable while the write operation is being carried out.
The write operation includes a verify operation in which it is determined whether programming or erasing progresses to a respective given level. The verify operation is essentially the same as the read operation. There is a case where the read operation is carried out during the verify operation. However, this case flows a larger current than the current that flows when either the verify operation or the read operation is carried out in the circuit configuration in which the ground line is used commonly to the read and write operations. The larger current develops a larger voltage drop across the parasitic resistance. Thus, the source potential of the specified memory cell in the read or write operation becomes higher than that obtained when only one of the read and verify operations is executed. This reduces the cell current. As a result, the read speed and the margin are degraded in the read or verify operation.